Automatic test pattern generation (ATPG) is used to identify test sequences that can be applied to test circuits on a chip to determine whether they function correctly. Conventional ATPG applies mathematically generated test patterns to targeted circuitry and logic of the chip commonly referred to as the “design under test” (or simply “DUT”). ATPG testing typically involves supplying a test pattern to the DUT using a series of flip-flops arranged in a scan chain configuration. Once test data is applied to the DUT, the output of the circuitry being tested is checked to see whether it matches an expected value. If it does not, a defect can be assumed.
A scan chain configuration includes multiple flip-flops connected in a sequential manner. These flip-flops are signaled by a “scan enable” signal to operate in two different modes: (1) a shift mode, and (2) a capture mode. In shift mode, a test pattern of data is shifted into the flip-flops in the chain one bit at a time. Once the test pattern is entirely shifted into flip-flops, the scan enable signal can switch to the capture mode during which testing of the DUT is performed by passing the shifted-in test value to the DUT. The DUT's output can then be analyzed to the see whether an expected value was returned. A single chip may have myriad DUTs requiring many chains of flip-flops spread across the chip to shift in the test pattern. The test pattern must be clocked in to the various flip-flops, and different test patterns will use different clock frequencies. So each DUT may require its own unique clock signal to ensure proper testing.
On-chip clock controllers (referred to herein simply as OCCs) are used on semiconductor chips to control the clocks in shifting and capturing data in and out of scan chain flip-flops. Conventional OCCs receive a clock signal unique to a particular clock domain of a chip and synchronize that clock signal with a testing clock signal using one or more shift registers. Unfortunately, the unique clock signals of the various OCCs on a chip become de-synchronized relative to each other because each OCC typically has its own set of synchronizing registers—which may differ in quantity, type or size from other OCCs on the chip—and independently synchronize their own clock signals at different times. Disparate OCCs with different synchronizing registers operating on different scan chains will cause errors in testing because the OCCs will operate independently.
Unsynchronized OCCs affect the quality of testing that can be performed using scan chains. They also make it difficult to accurately estimate power consumption for designs requiring more than one OCC because the predicted switching activity generated by simulations of the circuitry may be inaccurate. This is largely due to the occurrence of test clock pulses in each of the clock controllers that often result in two or more clock controllers pulsing at the same time and generating a spike in the power requirements of the circuitry being tested. The negative effects of such spiking behavior compound as the size of a system on chip (SoC) and the number of interacting clock domains therein increases.